1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to the fabrication of conductive interconnect lines by means of an in situ damascene process.
2. Description of the Related Art
The need for high performance semiconductor chips has continued to increase over the past several years, while at the same time the functionality of the circuitry has become more complex and the amount of area per chip has decreased. One approach to increase the speed and performance of the semiconductor chip is to reduce the size of the individual integrated circuit components. In modem integrated circuits, the channel length, and thus the gate length, of a typical field effect transistor (FET) is scaled down to a size of 0.2 xcexcm and less to reduce the switching speed of the FET elements sufficiently in order to allow, for example, a central processing unit (CPU) to operate with clock frequencies of up to 1 GHz and above. With small feature sizes, the performance of the semiconductor chips is not only limited by the switching speed of individual FET elements, but also by the electrical conductivity of the metal interconnects electrically connecting the various individual components and by the parasitic capacitances associated with the metal interconnects. In order to take full advantage of transistor elements capable of operating at fast speeds and exhibiting smaller feature sizes, the metal interconnects must be highly conductive and/or the parasitic capacitance between adjacent interconnect lines or vias should be kept as low as possible.
A typical process for surface wiring the individual components of an integrated circuit, also referred to as xe2x80x9cmetallization,xe2x80x9d is the so-called damascene process in which trenches and/or vias are formed in an insulating layer and are subsequently filled with a conductive material to form the conductive lines interconnecting the individual components of the integrated circuit. Currently, most of the silicon-based semiconductor chips comprise a metallization layer including silicon dioxide as a dielectric material and aluminum as the conductive material due to aluminum""s excellent adhesion to the surrounding silicon dioxide without any tendency to diffuse into the silicon dioxide. For integrated circuits having critical feature sizes of 0.5 xcexcm and less, the so-called interconnect delay caused by the limited conductivity of the metal lines and the relatively high dielectric constant of the silicon dioxide begins to dominate the switching speed of individual semiconductor elements. Thus, great efforts have been made to replace the metal and/or the dielectric by an appropriate material so as to reduce the RC constant defined by the resistivity of the conductive lines and the parasitic capacitance between adjacent lines.
Recently, copper has been proven to be a promising candidate for replacing the aluminum due to its lower specific resistivity, which is about half of aluminum. Moreover, contrary to aluminum, copper does not show eutectic reactions and thermally induced electromigration when used in very large scale integration (xe2x80x9cVLSIxe2x80x9d) and ultra-large scale integration (xe2x80x9cULSIxe2x80x9d) semiconductor chips. Additionally, copper is capable of being deposited at low temperatures with high aspect ratios, thereby yielding a good step coverage. The use of electrochemical deposition techniques for copper deposition is especially appealing due to low cost, high throughput, high quality of the deposited copper film, and excellent via/trench filling capabilities.
Furthermore, efforts have been made to replace silicon dioxide, which exhibits a dielectric constant of 3.8 and more depending on the deposition process, by appropriate materials having a significantly lower dielectric constant. As previously explained, in order to provide a highly reliable integrated circuit, the metal of the interconnect lines has to sufficiently adhere to the surrounding dielectric material, and diffusion of the metal atoms into the dielectric material must be reduced as much as possible. Thus, in many cases the metal may not be directly deposited onto the dielectric material. Instead, a barrier layer has to be deposited on the surface of the dielectric layer prior to deposition of the metal. For example, copper readily diffuses into silicon dioxide and does not adhere to silicon dioxide very well. Accordingly, a thin barrier layer, for instance comprising tantalum, is deposited to provide for sufficient adhesion of the copper and to prevent diffusion of the copper into the silicon dioxide.
A particularly serious issue in a damascene process is the generation of voids at the interface of the dielectric and the conductive material, especially at the bottom of vias formed in the conductive material that provide electrical contact to a previously formed metallization layer. In the damascene process using silicon dioxide and copper, a barrier layer is first deposited and, in order to avoid surface oxidation, a subsequent copper seed layer is formed in an in situ process, i.e., the same tool is used without breaking the vacuum between the deposition of the barrier layer and the copper seed layer. The synthesis of the barrier layer and the copper seed layer, however, results in stress-related damage, mainly in the form of voids. In particular, the voids generated at the bottom of a via that may establish contact to an underlying metal island or metal line are a significant reliability risk due to the degraded capability of conducting current to underlying components.
Although the crystal damage may be healed to some degree by an annealing process after deposition of the copper seed layer, the annealing step is a time-consuming process, and it has been observed that voids under or in vias cannot sufficiently be eliminated even by a long-lasting annealing process.
In view of the above, it is an object of the present invention to provide an effective method to significantly reduce void generation during a damascene metallization process.
According to one aspect of the present invention, an in situ method of forming a barrier metal layer on a substrate including a layer of dielectric material is provided, wherein the method comprises cleaning the surface of the substrate and depositing, in a plasma ambient, the barrier material on the surface of the substrate to form the barrier metal layer. Additionally, the method comprises controlling a temperature of the surface below a predefined critical temperature so as to inhibit void generation in the barrier metal layer.
According to another aspect of the present invention, an in situ method of forming a barrier metal layer on a substrate including a layer of dielectric material is provided, wherein the method comprises cleaning the surface of the substrate and depositing, in a plasma ambience, a barrier material on the surface of the substrate to form the barrier metal layer. Additionally, the method comprises performing at least one sequence interrupt, each of which defines a time period of reduced deposition activity on the surface, wherein the at least one sequence interrupt substantially avoids the generation of voids underneath the barrier metal layer.
According to a further aspect of the present invention, an in situ method of forming a barrier metal layer above a surface of a substrate comprises cleaning the surface of the substrate and depositing, in a plasma ambient, a barrier metal layer on the surface of the substrate. The method further comprises providing thermal contact from a source of coolant to a substrate and controlling a cooling power transferred from the source of coolant to the substrate to inhibit formation of voids in the barrier metal layer.
It should be noted that the term xe2x80x9cbarrier metalxe2x80x9d used herein is intended to include metallic barrier materials, such as titanium and tantalum, as well as non-metals, such as tantalum nitride and titanium nitride, in conformity with the standard semiconductor terminology.